HP OpenVMS Systems Documentation
OpenVMS Debugger Manual
16.3 Examining and Depositing into Vector Registers
The following sections explain how to examine and deposit into the
vector control registers (VCR, VLR, and VMR) and the vector registers
(V0 to V15).
The VAX architecture provides 16 vector registers (V0 to V15) and 3 vector control registers (VCR, VLR, and VMR). When referencing any of these registers in a debugger command, use the following built-in symbols (the register name preceded by a percent sign (%)):
As with all debugger register symbols, you can omit the percent sign
(%) prefix if your program has not declared a symbol with the same name.
The vector count register (VCR) specifies the length of the offset vector generated by the IOTA instruction.
The value of VCR is an integer from 0 to 64. By default, the debugger treats VCR as a longword integer. You can deposit values greater than 64 into VCR, but the debugger issues a diagnostic message that the value is out of bounds in such cases.
The following command sequence shows how to manipulate the value of VCR:
16.3.3 Examining and Depositing into the Vector Length Register
The vector length register (VLR) limits the highest element of a vector register that is processed by a vector instruction. The value of VLR is an integer from 0 to 64. This value specifies the number of register elements that are processed, starting with element 0.
In the context of a debugging session, the current value of VLR limits the highest element of a vector register that you can access with an EXAMINE or DEPOSIT debugger command.
The following command sequence shows how to manipulate the value of VLR to examine different numbers of elements of the vector register V1:
You cannot access a register element outside the range from 0 to VLR--1. In the following example, the EXAMINE command specifies element 7 of register V1, which is out of bounds (Fortran array syntax):
By default, the debugger treats VLR as a longword integer. You can
deposit values greater than 64 into VLR, but the debugger issues a
diagnostic message that the value is out of bounds in such cases.
The vector mask register (VMR) specifies a mask (a bit pattern) that a vector instruction uses to operate on only certain elements of a vector register operand. A masked vector instruction cannot operate on an element of a vector register that is masked by VMR.
VMR has 64 bits (1 quadword) numbered 0 to 63. Each bit corresponds to an element of a vector register. The value of a particular bit (0 or 1) determines whether the corresponding register element is operated on during a masked operation.
To examine one or more specific elements (bits) of VMR, use the same technique that you use to examine an array variable. (See Section 4.2.3.)
For example, the output of the following command shows that bit 5 of VMR is set (Fortran array syntax):
By default, when you examine VMR without specifying subscripts, the debugger displays the value of the register as a quadword integer in hexadecimal format to reduce the size of the output display. For example:
By specifying the EXAMINE/BIN %VMR or EXAMINE %VMR(0:63) command, you can display the value of each bit of VMR in a 64-row array format.
As with an array variable, you can deposit a value into one bit of VMR at a time. For example:
When specifying an element of VMR in a language expression, remember that VMR is an array of bits. You might have to temporarily set the language to one that allows bit operations, such as C or BLISS. For example:
16.3.5 Examining and Depositing into the Vector Registers (V0 to V15)
There are 16 vector registers, designated V0 to V15. Each of the vector registers has 64 elements, numbered 0 to 63, and each element has 64 bits (one quadword).
To examine one or more elements of a vector register, use the same technique that you use to examine an array variable. (See Section 4.2.3.) The examples in this section use Fortran array syntax:
The values of register elements are displayed in an indexed format similar to that used for an array variable. For example, the following command displays the values of elements 1 to 3 of register V1:
You cannot examine a range of vector registers. For example, the following commands are invalid:
The current value of the vector length register (VLR) limits the highest register element that you can examine or deposit into. (See Section 16.3.3.) Therefore, the following commands are equivalent:
The expression 0:%VLR--1 specifies the range of register elements that are denoted by the current value of VLR.
By default, the debugger treats each element of a vector register as a longword integer and displays the value in the current radix. For example:
However, note that a register value that is examined in the context of a vector instruction (that is, as an instruction operand) is displayed in the data type that is appropriate for the instruction (see Section 16.4.1).
To display the full (quadword) value of an element of a vector register as a quadword integer, use the EXAMINE/QUADWORD command. Similarly, to deposit a quadword integer value into a register element, use the command DEPOSIT/QUADWORD.
You can also use any of the other type qualifiers associated with the EXAMINE and DEPOSIT commands (for example, /FLOAT) to override the default type. For example:
You can use register symbols in language expressions subject to the restrictions on using aggregate data structures in language expressions. (See Section 188.8.131.52.) For example, the following expression is valid (Fortran syntax):
However, the following expression is not valid because more than one register element is specified:
16.4 Examining and Depositing Vector Instructions
The techniques for manipulating vector instructions include all of those used for scalar instructions (described in Section 4.3) and additional techniques specific to vector instructions:
Whether you are examining or depositing vector instructions, the debugger correctly processes the vector instruction qualifiers according to the instructions to which they apply. The following table summarizes the functions of these qualifiers. See the VAX MACRO and Instruction Set Reference Manual for complete information about their use.
16.4.1 Examining Vector Instructions and Their Operands
When you examine a program location that contains a vector instruction, the debugger decodes that instruction and translates it and its operands into their MACRO assembler form with the following restrictions (see the OpenVMS MACRO and Instruction Set Reference Manual for details about instruction opcodes):
The command EXAMINE/OPERANDS .%PC enables you to display the instruction at the current PC value and its operands. (See Section 4.3.1.) When you examine a vector instruction with this command, the values of any vector register operands are displayed as for an array variable. For example (Fortran array syntax):
As with scalar instructions, operand values are displayed in the data type that is appropriate for the examined instruction.
When you use the EXAMINE/OPERANDS command, the display of register elements depends on the following factors:
These concepts are shown in the following two examples, which show an unmasked and a masked register-to-register operation, respectively.
In this example, the examined instruction, VVADDF, is performing an unmasked operation so that the current value of VMR is irrelevant. All elements from 0 to 5 are displayed.
In the next example, the same VVADDF instruction is performing a masked operation. The instruction qualifier /1 specifies that elements that match the set bits (bit value 1) in VMR are operated on.
The next example shows a masked operation that loads data from memory to a vector register. Comments, keyed to the callouts, follow the example.
The following comments refer to the callouts in the previous example:
Figure 16-1 Masked Loading of Array Elements from Memory into a Vector Register
Note the following information when depositing vector instructions (see the OpenVMS MACRO and Instruction Set Reference Manual for details about instruction opcodes):
16.5 Using a Mask When Examining Vector Registers or Instructions
Section 16.4.1 explains how the command EXAMINE/OPERANDS .%PC displays vector instruction operands, depending on whether or not the operation is masked by the vector mask register (VMR).
This section explains how to specify an arbitrary mask in order to simulate or override the effect of VMR and obtain the following results:
You specify a mask by using either the /TMASK or /FMASK qualifier with the EXAMINE command.
The /TMASK qualifier applies the EXAMINE command only to the elements of the examined register that correspond to the set bits (bit value: 1) of the mask. The /FMASK qualifier applies the EXAMINE command only to the elements that correspond to the clear bits (bit value: 0) of the mask.
The current value of VLR limits the highest element of a vector register that you can examine. However, the value of VLR does not affect examining an array in memory.
You can optionally specify a mask (in the form of a mask address expression) with the /TMASK and /FMASK qualifiers. For more information: